Exemplary embodiments relate to a semiconductor memory device and, more particularly, to a semiconductor memory device including memory blocks coupled to bit lines.
A semiconductor memory device includes memory cells coupled to bit lines and configured to store data. The memory cells are classified into memory blocks. A sense circuit (or a page buffer) stores data in the memory cells by controlling the voltages of the bit lines on the basis of external data when a program operation is performed and reads data stored in the memory cells by sensing the voltages of the bit lines when a read operation is performed.
Meanwhile, in order to increase the data storage capacity, the number of memory cells increases as well. The length of the bit lines may increase, while an interval between the bit lines narrows. For this reason, parasitic capacitance between adjacent bit lines is increased in proportion to the length of the bit line and an interference phenomenon occurs between the adjacent bit lines, resulting in a low operating speed.
For example, in a program operation, unselected bit lines of even bit lines and odd bit lines are precharged, and voltage supplied to selected bit lines is determined depending on data to be stored in memory cells. Furthermore, in a read operation, after selected bit lines are precharged and unselected bit lines are discharged, data stored in memory cells is read by sensing a change in the voltages of the selected bit lines.
As the length of the bit lines increases, the precharging speed of the bit lines becomes slow. Accordingly, it takes more time to fully precharge the bit lines, and the operating speed becomes slow.